//////////////////////////////////////////////////////////////////////////
// not change field
`define MAX_SRC_P               80

`define PIPE_BUFFER_SIZE        128
`define PIPE_AM_LEVEL           120
`define PIPE_BUFFER_PTR_WIDTH   7

`define ROOT_ID                 0

`define DST_ID_DWIDTH           32
`define DST_ID_ST               0

`define EDGE_OFF_DWIDTH         32
`define EDGE_OFF_ADDR_ST        0

`define SRC_ID_DWIDTH           32
`define EDGE_INFO_ADDR_ST       100000000

`define SRC_P_AWIDTH            32

`define DEGREE_DWIDTH           32

`define MEM_AWIDTH              32
// MEM_DWIDTH 最大值为 512
`define MEM_DWIDTH              512
`define MEM_PER_DWIDTH          32

`define MEM_EDGE_WIDTH          32
`define MEM_EDGE_ST             0

`define ACC_INI_CYCLE           100
`define RST_INI_CYCLE           50

`define DIV_DELAY 15
`define ADD_DELAY 11
`define ACCUMULATOR_DELAY 21
/////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////
// change field
// 所有值会随着点边流水线的变化而改变
// bram 数量会随之改变以降低扇入扇出
`define VERTEX_PIPE_NUM         16  // set to 16.
`define EDGE_PIPE_NUM           32  // set to 32.
`define VERTEX_PIPE_NUM_WIDTH   4   // log2(VERTEX_PIPE_NUM)

`define VERTEX_BRAM_NUM         64  // set to 64.
`define VERTEX_BRAM_NUM_WIDTH   6   // log2(VERTEX_BRAM_NUM)
`define VERTEX_BRAM_AWIDTH      16  // 2^22 / VERTEX_BRAM_NUM
`define VERTEX_BRAM_DWIDTH      16  // set to 8.


// 用于选择器，从 32 结果中选出1个正确结果
`define VERTEX_MASK_WIDTH       5   // log2(EDGE_PIPE_NUM)

// 用于累加器，并行归并
`define ACC_ID_WIDTH            5   // log2(VERTEX_PIPE_NUM) + 1
`define TOT_ACC_ID_WIDTH        160 // EDGE_PIPE_NUM * ACC_ID_WIDTH
`define EDGE_MASK_WIDTH         1   // set to 1.
`define TOT_EDGE_MASK_WIDTH     32  // EDGE_PIPE_NUM * EDGE_MASK_WIDTH


`define REQ_WIDTH               5   // log2(EDGE_PIPE_NUM)

/* not used
`define REUSE_WIDTH 5
`define TOT_REUSE_WIDTH 160
*/

`define REORDER_LOC_Y_WIDTH     5   // log2(EDGE_PIPE_NUM)
`define TOT_REORDER_LOC_Y_WIDTH 160 // EDGE_PIPE_NUM * REORDER_LOC_Y_WIDTH
// 16 个点流水线写回 64 个 bram
`define WB_VALID_WIDTH          4   // VERTEX_BRAM_NUM / VERTEX_PIPE_NUM
/////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////
// for channel
`define OFFSET_CHANNEL_WIDTH        512 // read width default is 512bit.
`define INFO_CHANNEL_WIDTH          512 // read width default is 512bit.
`define DEGREE_CHANNEL_WIDTH        512 // read width default is 512bit.
`define VERTEX_DATA_CHANNEL_WIDTH   256 // VERTEX_PIPE_NUM * VERTEX_BRAM_DWIDTH
`define VERTEX_ID_CHANNEL_WIDTH     128 // VERTEX_DATA_CHANNEL_WIDTH
`define CYCLE_CHANNEL_WIDTH         32  // set to 32.
/////////////////////////////////////////////////////////////////////////